Real-time FPGA processing

Designed during the ANR FAON project, this platform is a prototype for 1Gbit/s QAM receiver for the optical access networks with Frequency Division Multiplexing (FDM). This prototype is based on a Virtex 7 FPGA and four analog to digital convertors sampling at 1 Gsps. This real-time prototype validates our algorithms for equalization and synchronization, but also a new FPGA design flow based on HLS (High Level Synthesis) and finally, the feasibility of frequency multiplexing for access networks. The prototype has been realized in collaboration with UMR CNRS FOTON for the RF front-end and Orange Labs for the integration in the system and the tests. The Granit team has designed the algorithms for demodulation as well as the FPGA implementation.

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